Digital Control of Power Electronics
Digital Power Electronics introduces practical digital control for power converters. The course starts with a quick refresher on continuous-time control, then develops proportional, integral, PI/PID, and lead-lag compensators. These are applied to voltage- and current-loop design for buck, boost, and buck-boost converters with emphasis on tuning and stability in the frequency domain. It concludes with single-phase and three-phase PLL techniques for grid-connected systems, including quadrature generation and frequency/phase estimation.
Modules
Description: Basics of continuous‑time control: Laplace‑domain modeling, transfer functions, poles/zeros, and how ζ and ωₙ set step and Bode responses. Includes worked examples on second‑order systems to connect pole locations to time‑ and frequency‑domain behavior.
Description: Integrator, single‑pole, and single‑zero building blocks and their Bode magnitude/phase slopes. Shows how break frequencies shape response when you combine elements.
Description: Z‑transform fundamentals for digital control: FIR/IIR structures, pole‑zero plots in the z‑plane, and stability via the unit circle. Implements a moving‑average FIR and a trapezoidal (Tustin) integrator from the difference equation.
Description: Designing a discrete‑time P controller: derive the closed‑loop characteristic, place roots via K, and read stability from the unit circle. Compares overdamped vs underdamped step responses as K increases.
Description: Integral controller in discrete time to eliminate steady‑state error. Form open‑/closed‑loop transfer functions, find the stability range for Ki, and examine pole locations vs sample time.
Description: Continuous‑time PI design and digital implementation using the Tustin (bilinear) transform. Place the zero, tune Kp/Ki for the target bandwidth, and compare continuous vs digital closed‑loop responses.
Description: PID controller with two zeros and an integrator: pick Kp, Ki, Kd for a desired bandwidth and damping. Convert to a digital controller via Tustin and verify the resulting z‑domain poles and step response.
Description: Lead–lag controller with integral action: pick phase margin and bandwidth, then solve for fz, fp, and gain. Validate the design on a sample plant with Bode plots.
Description: Voltage‑mode control of a CCM buck converter: derive the plant, choose target fc and phase margin, and compute lead/lag corner frequencies and gain. Includes code to evaluate gain/phase at fc and back out controller parameters.
Description: Digital implementation of the buck converter voltage loop: discretize the continuous controller with backward‑Euler and Tustin, generate z‑domain transfer functions, and compare responses.
Description: Current‑mode control of a buck converter: use the reduced‑order plant vo/iL, select bandwidth and phase margin, and design a lead/lag form. Check gain/phase at fc and predict time‑domain response.
Description: Digital current‑mode control of a buck: discretize the analog design, form z‑domain controllers, and obtain coefficient sets for implementation.
Description: Voltage‑mode control of a boost converter: derive the plant, select fc and phase margin, and compute controller zero/pole locations and gain.
Description: Digital voltage loop for a boost converter: convert the continuous controller to z‑domain (backward‑Euler/Tustin) and compare behavior.
Description: Current‑mode control of a boost converter: form the vo/iL plant, design a lead/lag controller for the target bandwidth, and verify margins.
Description: Digital current‑mode control for boost: discretize the analog controller and produce implementable z‑domain coefficients.
Description: Voltage‑mode control of a CCM buck converter: derive the plant, choose target fc and phase margin, and compute lead/lag corner frequencies and gain. Includes code to evaluate gain/phase at fc and back out controller parameters.
Description: Voltage‑mode control of a CCM buck converter: derive the plant, choose target fc and phase margin, and compute lead/lag corner frequencies and gain. Includes code to evaluate gain/phase at fc and back out controller parameters.
Description: Current‑mode control of a buck converter: use the reduced‑order plant vo/iL, select bandwidth and phase margin, and design a lead/lag form. Check gain/phase at fc and predict time‑domain response.
Description: Current‑mode control of a buck converter: use the reduced‑order plant vo/iL, select bandwidth and phase margin, and design a lead/lag form. Check gain/phase at fc and predict time‑domain response.
Description: Single‑phase PLL architecture: PFD models, loop filter plus integrator, and open‑/closed‑loop transfer functions. Pick bandwidth/phase margin and validate with Bode plots and time‑domain lock behavior.
Description: Single‑phase PLL implemented in fixed‑point (Q‑format): discretize the loop filter, compute digital coefficients, and prepare values appropriate for embedded implementation.
Description: Single‑phase PLL implemented in single‑precision floating point: derive digital loop‑filter coefficients and evaluate numerical behavior.
Description: Three‑phase PLL, Part 1: dq transformation, PI loop design for a chosen ζ and ωₙ, and analytical expressions for kp/ki.
Description: Three‑phase PLL, Part 2: discretize the PI loop (backward‑Euler/ZOH/Tustin) and extract floating‑point coefficients.
Description: Three‑phase PLL, Part 3: finalize digital coefficients (e.g., Tustin form) and summarize implementation parameters.